1. Technical Field
Various embodiments of the present invention relate to semiconductor apparatus, and related control methods. In particular, certain embodiments relate to a repair circuit and a control method thereof in a semiconductor memory apparatus.
2. Related Art
A semiconductor apparatus, more specifically a semiconductor memory apparatus, typically includes a repair circuit for storing information on a failed memory cell and replacing the failed memory cell with a redundant memory cell based on the stored information.
FIG. 1 is a block diagram of a semiconductor apparatus including a repair circuit according to the conventional art. As illustrated in FIG. 1, a semiconductor apparatus 1 according to the conventional art includes a memory block 10, a fuse set block 20, a NAND gate ND1, a decoder 30, and a column selection block 40.
The memory block 10 includes normal column lines NY<0:N> coupled to memory cells and redundant column lines RY<0:3>.
As the normal column lines NY<0:N> or the redundant column lines RY<0:3> for repairing the normal column lines NY<0:N> are activated, it is possible to perform an operation for recording data on a corresponding memory cell or reading the recorded data from the corresponding memory cell.
The fuse set block 20 includes a plurality of fuse sets fuse set 0 to fuse set 3.
The fuse set block 20 compares previously stored repair information with address signals A<3:9> in response to fuse control signals FC1 and FC2 and generates repair signals RYSb<0:3>.
The decoder 30 decodes the address signals A<3:9> and generates decoding signals NYb<0:N> for selecting one of the normal column lines NY<0:N>.
The NAND gate ND1 substantially prevents the decoder 30 from outputting the decoding signals NYb<0:N> if any one of the repair signals RYSb<0:3> is activated.
The column selection block 40 selects and activates the normal column lines NY<0:N> corresponding to the decoding signals NYb<0:N> or the redundant column lines RY<0:3> corresponding to the repair signals RYSb<0:3> in response to a strobe signal STROBE.
FIG. 2 is diagram illustrating the internal configuration of the fuse set illustrated in FIG. 1. As illustrated in FIG. 2, the fuse set 0 (21) includes an enable fuse 22, a plurality of address fuses 23, a comparator 24, and a NAND gate ND11.
The plurality of address fuses 23 output fuse signals FA<3:9> based on whether a fuse has been cut (or ruptured). That is, when the fuse has been ruptured, the plurality of address fuses 23 output the fuse signals FA<3:9> at a logic high level. When the fuse has not been ruptured, the plurality of address fuses 23 output the fuse signals FA<3:9> at a logic low level.
When the address signals A<3:9> are ‘0000000 (binary)’, none of the plurality of address fuses 23 is not ruptured. In such a case, it is not possible to identify whether the fuse set 0 (21) is not used or an address ‘0 (decimal number)’ is to be replaced.
In this regard, the enable fuse 22 is added in order to determine the use or non-use of the fuse set 0 (21). That is, a fuse is in the enable fuse 22 is ruptured or not, so that it is possible to store information on the use of the fuse set 0 (21) and information on the replacement of the address ‘0 (decimal number)’.
If the fuse has been ruptured, the enable fuse 22 outputs a fuse enable signal FUSE_EN at a logic high level. If the fuse has not been ruptured, the enable fuse 22 outputs the fuse enable signal FUSE_EN at a logic low level.
The comparator 24 compares the address signals A<3:9> with the fuse signals FA<3:9> and outputs a comparison signal CMP_SUM. That is, when the address signals A<3:9> match the fuse signals FA<3:9>, the comparator 24 outputs the comparison signal CMP_SUM at a logic high level. When the address signals A<3:9> do not match the fuse signals FA<3:9>, the comparator 24 outputs the comparison signal CMP_SUM at a logic low level.
The NAND gate ND11 activates the repair signal RYSb<0> to a logic low level if any one of the fuse enable signal FUSE_EN and the comparison signal CMP_SUM is at a logic high level.
The plurality of fuse sets fuse set 1 to fuse set 3 may have substantially the same configuration as that of the fuse set 0 (21).
FIG. 3A is a circuit diagram of the address fuse illustrated in FIG. 2. As illustrated in FIG. 3A, the address fuse 23 includes a plurality of inverters IV1 to IV3, a plurality of transistors M1 and M2, and a fuse.
FIG. 3B is a diagram illustrating the operation timing of the address fuse illustrated in FIG. 2. As illustrated in FIG. 3B, a fuse signal FA<#> is initialized to a logic high level in response to the fuse control signal FC1.
After the fuse control signal FC2 transits to a logic high level, if the fuse is ruptured, the fuse signal FA<#> is substantially maintained at a logic high level. If the fuse is not ruptured, the fuse signal FA<#> transits to a logic low level.
Each of the plurality of fuse sets fuse set 0 to fuse set 3, which are main elements of the repair circuit of the semiconductor apparatus 1 according to the conventional art as described above, further includes the enable fuse 22, in addition to the plurality of address fuses 23.
While the area occupied by the fuse in the semiconductor apparatus is large, since the conventional repair circuit needs the enable fuse in addition to the address fuses for actually storing address information, a circuit area may be increased.